The present invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device in which the peripheral circuits are constructed in such a manner as to minimize substrate current while also preventing the injection of hot electrons into the memory cells of the memory array thereof.
In general, semiconductor memory devices include an array of memory cells which are at least partially surrounded by peripheral circuits, including sense amplifiers, address buffers and decoders, I/O circuitry, and the like, which function to enable data to be written into and read from a particularly addressed one(s) of the memory cells. The peripheral circuits are generally CMOS circuits which are configured to absorb hot electrons generated by the outermost/N-channel transistor thereof before they can reach the memory cells, thereby preventing the destruction of the data stored in the memory cells.
With reference now to U.S. Pat. No. 4,497,043, the disclosure of which is incorporated herein by reference thereto, a conventional CMOS peripheral circuit will now be described. More particularly, with additional reference to FIG. 1, there can be seen a semiconductor memory device which includes a CMOS peripheral circuit B which is essentially identical to the one shown in FIG. 2 of U.S. Pat. No. 4,497,043. The semiconductor memory device includes a memory cell array A which is flanked by the CMOS peripheral circuit B. Each individual memory cell Q1 of the memory cell array A includes a transfer gate 18 and a storage capacitor 26. The peripheral circuit B includes a P-channel transistor Q3 formed in an N-type well 38 which is formed in a P-type semiconductor substrate 10, and an N-channel transistor Q2 formed directly in the substrate 10 outside of the P-channel transistor Q3. A power supply voltage Vdd, e.g., 5 volts, is applied to a highly concentrated N-type region 48 separately formed in the N-type well 38, and a negative substrate bias voltage Vbb is applied to the substrate 10.
The storage electrode 20 of the memory cell capacitor 26 is also connected to Vdd, to thereby form an inversion layer 24 beneath the dielectric layer 22 of the capacitor 26. Binary data is represented by the presence or absence of an electron in the inversion layer 24, e.g., a "1" bit is represented by the presence of an electron in the inversion layer 24, and a "0" bit is represented by the absence of an electron in the inversion layer 24. The gate electrode 14 of the transfer gate 18 of each memory cell Q1 constitutes an extension of a word (row) line which is connected to a voltage source WL which goes high during a memory read/write operation, to thereby form an inversion layer in the channel region between the source/drain electrode 16 and the inversion layer 24, beneath the gate insulation layer 14, in order to thereby transfer data into/from the accessed memory cell Q1 from/to the peripheral circuit B.
Further, during a memory read/write operation, the transistors Q2 and Q3 of the peripheral circuit B are activated, which results in hot electrons 36 generated by the N-channel transistor Q2 being injected into the substrate 10. These hot electrons 36 are substantially absorbed or captured by the N-well 38, to thereby prevent these hot electrons 36 from reaching the memory cell Q1 to destroy the integrity of the data stored therein.
With reference to FIG. 2, there can be seen a block diagram depicting the general lay-out of the conventional memory device shown in FIG. 1, wherein the memory cell array A is completely surrounded by regions 50 which include the P-channel transistors Q3 of the peripheral circuit B, and regions 52 which include the N-channel transistors Q2 of the peripheral circuit B. With reference to FIG. 2, it can be more easily visualized how the P-channel transistors Q3 serve to absorb minority carriers generated by the N-channel transistors Q2 to prevent them from reaching the memory cell array A.
Although the CMOS peripheral circuit of the above-described conventional memory device does function to prevent hot electrons from reaching the memory array, it suffers from the following drawback. More particularly, holes in the substrate 10 tend to combine with the injected hot electrons 36 to form electron-hole pairs which increase substrate current, which, in turn, disadvantageously decreases the threshold voltage of the memory cells Q1 of the memory cell array A, thereby lowering the noise immunity of the memory cells Q1 and lowering the electrical insulation between adjacent memory cells Q1 of the memory cell array A. Consequently, the integrity of the data stored in the memory cell array A is degraded.
Based upon the above and foregoing, it can be appreciated that there presently exists a need in the semiconductor art for a semiconductor memory device which eliminates the above-described shortcomings and disadvantages of the presently available semiconductor memory devices. The present invention fulfills this need.